Here is a summary of the material covered in this chapter:

Switching circuits are significantly different than linear circuits. They are also easier to understand. Before we look at more complex circuits, we will begin the discussion by introducing discrete solid-state switching circuits: those built around BJTs, FETs, and MOSFETs.

A BJT switch consists of a transistor that is driven back and forth between saturation and cutoff. A simple BJT switch is shown in Figure 19-1. When the input equals , the base-emitter junction is biased off. This is illustrated by the load line shown in the figure. When the BJT is in cutoff, the circuit (ideally) has the following values:

This operating state is analogous to an open switch. When the input equals , the transistor is driven into saturation and the following conditions occur:

This operating state is analogous to a closed switch.

 

FIGURE 19-1 A basic BJT switch and its load line.

The characteristics listed for a BJT switch assume that:

1. is low enough to drive the transistor into cutoff.
2. must produce enough base current to drive the transistor into saturation.
3. The transistor is an ideal component.
   

These conditions can be assured by designing the circuit so that:

Condition 1 guarantees that the circuit will driven into cutoff by the input. Conditions 2 and 3 assure that the transistor will be driven into saturation. Example 19.1 of the text demonstrates the relationship between the input and output voltages for a BJT switch.

The practical BJT switch differs from the ideal in several aspects. In practice, at cutoff. Even at cutoff there is some leakage current through the circuit. Typically, falls within 1 V of at cutoff. Further, at saturation. There is always some voltage dropped across the transistor's internal resistance. Typically, falls between 0.2 and 0.4 V at saturation. These variations from the ideal are quite minor, so we can assume ideal conditions when analyzing or designing a BJT switch.

The basic JFET switch varies from the BJT switch in several ways.

1. The JFET circuit has a much higher input impedance.
2. A negative input pulse produces a positive output pulse (assuming the component is an n-channel JFET).

Both of these points are illustrated in Figure 19-2.

 

FIGURE 19-2 A JFET switch.

In order to understand the relationship between the input and output signal polarities, we need to consider some basic characteristics of JFETs. When:

        and       

Assuming the value of is chosen so that , will equal 0 V when . When the input goes to :

        and       

This assumes that is equal to (or more negative than) . As with the BJT switch, practical circuit current and voltage values vary only slightly from ideal values. The analysis of a JFET switch is demonstrated in Example 19.2 of the text.

The MOSFET switch has the high input characteristics of the JFET switch. At the same time, the input and output voltages have the same polarity (as shown in Figure 19-3). The transconductance curve in Figure 19-3 shows that when .

In this case, the output is found as:

When goes positive, increases and decreases. This results in the output waveform shown in Figure 19-3.

There is a tradeoff that must be considered in the design of a MOSFET switch. If the circuit is designed with a lower value of , then comes closer to the value of when . This relationship is illustrated in Example 19.3 of the text. The problem is this: With a lower value of , the value of may not be great enough to drop to 0 V when goes positive. Using a CMOS switch eliminates this problem.

 

FIGURE 19-3 The MOSFET switch.

The CMOS switch (introduced in Chapter 13) eliminates the tradeoff caused by . A CMOS switch is shown in Figure 19-4. The two MOSFETs are always in opposite operating states, as illustrated in the table below:

State	State	Resistance	Resistance
On	Off	Low	High
Off	On	High	Low

When is on and is off, the resistance combination in the table results in an output that is very close to 0 V. When is off and is on, the resistance combination in the table results in an output very close to . This is why CMOS switches are almost always used.

 

FIGURE 19-4 The CMOS switch.

One common application for a simple BJT (or any other) switch is as an LED driver. An LED driver is shown in Figure 19.9 of the text. The driver shown in this figure is used to couple a low-current circuit to a relatively high-current device (the LED). When the output from the low current circuit is low (0 V), the transistor is in cutoff and the LED is off. When the output from the low current circuit goes high (+5 V), the transistor is driven into saturation and the LED lights. The driver is used because the low-current device does not have the current capability to supply the 1 mA (typical) required to light the LED.

Any waveform made up of alternating (high and low) dc voltages is referred to as a rectangular waveform. The time spent in the high state is called the pulse width (PW) and the time spent in the low state is called the space width (SW). The sum of the PW and SW is called the cycle time (). A square wave is a special-case rectangular waveform where the PW and SW are equal.

In an ideal rectangular waveform, the transition from one state to another would be instantaneous and the waveforms would look like true rectangles (or squares), as shown in Figure 19-5. The relationships between PW, SW, and for an ideal waveform can be expressed as:

     

In practical waveforms, the transitions are not instantaneous and the question arises as to when a particular state ends and another begins. In order to avoid confusion, a standard has been accepted as to where measurements are taken. All measurements for PW, SW, or are made at the 50% points on the transitions (see Figure 19-5). PW and measurements are demonstrated in Example 19.4 of the text.

 

FIGURE 19-5 Measuring pulse width, space width, and cycle time.

Another time-related measurement relating to rectangular waves is duty cycle. Duty cycle is the ratio of pulse width to cycle time expressed as a percentage. By formula:

The duty cycle of a waveform tells us the percentage of the waveform that is spent in the high state. As you would imagine, a square wave (PW = SW) has a 50% duty cycle. Example 19.5 of the text demonstrates the duty cycle calculation for a waveform.

Figure 19-6a represents an ideal waveform applied to the base (input) of a BJT switch. Figures 19-6b and 19-6c show the resulting collector (output) current and voltage waveforms. There are two important points you should notice about the output waveforms:

1. There is a delay between each input transition and each output transition.
2. The output transitions are not instantaneous (vertical). In other words, it takes some measurable amount of time for the transitions to occur.

 

FIGURE 19-6 The causes of propagation delay.

The overall time delay between input and output transitions (measured at the 50% points) is called propagation delay. There are four transistor switching times that contribute to propagation delay. These times can be defined as follows:

1. Delay time () is the time required for the BJT to come out of cutoff. As shown in Figure 19-6, this is the time required for to drop to 90% of its high-state value.
2. Rise time () is the time required for the BJT to make the transition from cutoff to saturation. As shown in Figure 19-6, rise time is measured from the 90% to the 10% points on the waveform.
3. Storage time () is the time required for the BJT to come out of saturation. As shown in Figure 19-6, this is the time required for the to reach 10% of its high-state value.
4. Fall time () is the time required for the BJT to make the transition from saturation to cutoff. As shown in Figure 19-6, fall time is measured from the 10% to the 90% points on the waveform.

The times are defined (above) in terms of transistor collector voltage because they are commonly measured with an oscilloscope.

It should be noted that delay time and storage time account for the delay between input and output transitions. Rise time and fall time account for the transition slopes. This point is illustrated in Figure 19.13 of the text.

The spec sheet for the 2N3904 gives us the following values:

(as listed in Figure 7.24 of the text). As you can see, the transistor takes much longer to switch from saturation to cutoff than it takes to switch from cutoff to saturation. (The reason for this is dealt with later in the chapter.) If the above values are added, we get a theoretical minimum switching time of 320 ns. This time can be used to calculate a theoretical maximum switching frequency as follows:

In practice, this is a far higher frequency than the 2N3904 is capable of. In Appendix D of the text, a relationship between the upper cutoff frequency of a transistor and its rise time is derived:

Using this equation, the actual upper cutoff frequency for the 2N3904 is found as:

At first glance, it appears that is quite a bit higher than the value of calculated earlier. However, for a BJT to accurately reproduce a square wave input, the value of for the transistor needs to be at least 100 times the frequency of the input square wave. In other words, the practical limit on a switching circuit employing the 2N3904 is found using:

Figure 19.14 of the text illustrates what happens if the practical frequency limit of a switching circuit is exceeded. Example 19.6 demonstrates how to perform a frequency analysis on a BJT switching circuit.

Reducing delay time. When a BJT is in cutoff, the depletion layer is at its maximum width and. When the input to the BJT goes positive, the depletion layer starts to dissolve, allowing to begin increasing. Delay time () is the time required for to rise to 10% of . There are three factors that affect how long this takes:

1. The physical characteristics of the BJT.
2. The amount of reverse bias initially applied to the device.
3. The value of that the input signal generates when it goes positive.

We can't do anything about the physical characteristics of the device, but we can do several things to reduce .

If we keep the reverse-bias voltage to a minimum, then the width of the depletion layer is held to a minimum, decreasing . Also, if we can provide a very high initial value of, then is reduced even further. (A practical method of increasing the initial value of is introduced later in this chapter.)

Rise time. Rise time () is the time required for the collector current to rise from 10% to 90 % of . This is caused by the time required for the depletion layer to fully dissolve. It is a function of the physical characteristics of the device and there is nothing we can do to reduce its value.

Reducing storage time. The biggest overall delay is storage time (). When a BJT is in saturation, the base region is flooded with charge carriers. When the input goes low, it takes a long time for these charge carriers to leave the region and allow the depletion layer to begin to form. The amount of time this takes is a function of three factors:

1. The physical characteristics of the device.
2. The initial value of.
3. The initial value of reverse bias voltage applied at the base.

Once again, we can't do much about the first factor, but we can do something about the other two. If we can keep just below saturation, then the number of charge carriers in the base region is reduced and so is . We can also reduce by applying a high initial reverse bias to the transistor.

Fall time. Like rise time, fall time () is a function of the physical characteristics of the transistor, and there is nothing we can do to reduce its value.

Putting all these statements together, we see that delay and storage time can be reduced by:

1. Applying a high initial value of (to decrease delay time) that settles down to some value lower than that required to saturate the transistor (to reduce storage time).
2. Applying a high initial reverse bias (to reduce storage time) that settles down to the minimum value required to keep the transistor in cutoff (to reduce delay time).

It is possible to meet all of these conditions simply by adding a single capacitor to a basic BJT switch. This capacitor, called a speed-up capacitor, is connected across the base resistor as shown in Figure 19-7. The waveforms in the figure are the result of adding the capacitor to the circuit.

When initially goes high, the capacitor acts like a short circuit around. As a result, the input signal is coupled directly to the base for a brief instant. This results in a high initial voltage spike being applied to the base, generating a high initial value of . As the capacitor charges, decreases to the point where is held just below the saturation point.

When the input first goes negative, the charge on the speed-up capacitor briefly drives the base to –5 V. This drives the transistor quickly into cutoff. As soon as the capacitor discharges, the base voltage returns to 0 V. This ensures that the base-emitter junction is not heavily reverse biased. In this way, all of the desired criteria for reducing switching time are met.

 

FIGURE 19-7 Speed-up capacitor and resulting waveforms.

The value of the speedup capacitor () is chosen so that the RC time constant formed by and is very short compared to the pulse width of the input signal. This requirement is met by using the following equation to select :

     where     

One more point: The theoretical waveform in Figure 19-6 shows a positive voltage spike of +5 V being applied to the base. This is not possible, as the base-emitter junction starts to conduct and limits the voltage drop to approximately 0.7 V. This results in the actual waveform shown in the figure.

JFET spec sheets usually list values of , , , and . When this is the case, you can solve for in the same way that you did for BJTs. In some cases, only turn-on time and turn-off time are listed. When this is the case, use in place of in your calculations.

JFETs are voltage-controlled devices, so speed-up capacitors have less effect on delay times. They can reduce turn-off time—by supplying an initial voltage greater than —but do little to improve turn-on time.

So far, all the circuits we have discussed are inverters (which introduce a 180° phase shift from input to output). Another type of switching circuit is the buffer. Two such circuits are illustrated in Figure 19.18 of the text. Because the input and output are in phase, we must redefine our delay values as follows:

1. is the time required for to reach 10% of its maximum value.
2. is the time required for to rise from 10% to 90% of its maximum value.
3. is the time required for to drop to 90% of its maximum value.
4. is the time required for to drop from 90% to 10% of its maximum value.

Except for these differences, buffer and inverter circuits are nearly identical. A comparison of inverter and buffer switching times is provided in Figure 19.19 of the text.

The Schmitt trigger is very similar to the comparator. Both are voltage-level detectors, but the Schmitt trigger has several key differences from the comparator that result in these two circuits being used in very different applications. The response of a Schmitt trigger to a change in input voltage is illustrated in Figure 19-8. The following is a brief description of the waveforms shown:

1. When the input makes a positive-going transition past a specified voltage, the output of the Schmitt trigger goes from one voltage level () to the other (). The input voltage at which this change occurs is called the upper trigger point (UTP).
2. When the input makes a negative-going transition past a specified voltage, the output of the Schmitt trigger goes from to . The input voltage at which this change occurs is called the lower trigger point (LTP).

 

FIGURE 19-8 Schmitt trigger input and output signals.

The UTP and LTP levels are determined by the component values in the circuit. UTP and LTP values may or may not be equal, but the LTP value can never be greater (more positive) than the UTP value. An example of unequal trigger points is shown in Figure 19.21 of the text.

The output from a Schmitt trigger changes when:

• The UTP is reached by a positive-going transition
• The LTP is reached by a negative-going transition

Input voltage levels that fall between these two trigger points do not affect the output of the Schmitt trigger. Once the UTP is exceeded, the output will not change states until the input makes a negative-going transition that passes the LTP. The opposite is also true. Once the input drops below the LPT, the output will not change states until the input makes a positive-going transition that passes the UTP. (See Figure 19.22 of the text.) Note that the voltage difference between the UTP and LTP is often referred to as hysteresis.

The noninverting Schmitt trigger uses a simple feedback resistor connected as shown in Figure 19-9. Note that the only difference between this circuit and a linear inverting amplifier is that the input signal is applied to the noninverting input.

 

FIGURE 19-9 Noninverting Schmitt trigger operation.

The values of and are selected to set the trigger point values for the noninverting Schmitt trigger. Generally, the UTP and LTP values can be found as:

     and     

The value of depends on the load resistance and the supply voltages. As long as , we can assume that and . The use of these relationships is demonstrated in Example 19.7 of the text.

The noninverting Schmitt trigger in Figure 19-9 is limited in that it must have trigger points that are equal in magnitude (UTP = –LTP). The circuit can be modified as shown in Figure 19-10 to provide trigger points that are not equal in magnitude.

 

FIGURE 19-10 A noninverting Schmitt trigger designed for UTP and LTP

The key to the operation of this circuit is the fact that the two diodes (and) conduct on opposite transitions of the output. When the output is negative, conducts and is off. As a result, form the feedback path and the UTP is found using:

When the output is positive, conducts and is off. As a result, form the feedback path, and the LTP is found using:

As the two trigger points are determined by separate feedback paths, they need not be equal in magnitude. This concept is demonstrated in Example 19.8 of the text.

It is also possible to wire an op-amp as an inverting Schmitt trigger. Such a circuit is shown in Figure 19-11. The UTP and LTP values for the circuit are found using:

     and     

The use of these two equations is demonstrated in Example 19.9 of the text.

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