The JFET is a three-terminal device that contains two semiconductor materials and a single junction. The construction of the JFET can be represented as shown in Figure 12-1. As shown in the figure, the three terminals of the JFET are called the source, drain, and gate. The semiconductor material that connects the drain and source terminals is referred to as the channel. The channel is made up of one type of material, while the gate is made up of the other. Note that:

• A given JFET is identified by the type of material used as the channel. (The component in Figure 12-1 is referred to as an n-channel JFET.)
• The gate material surrounds the channel-like a belt around your waist. (The two p-type materials in Figure 12-1 are actually ends of the same material, as viewed from the side.)

 

FIGURE 12-1. N-channel JFET construction.

The commonly used JFET schematic symbols are shown in Figure 12-2. Note that:

• The arrow is positioned on the gate terminal and points toward the n-type material.
• N-channel JFETs require positive supply voltages, while p-channel JFETs require negative supply voltages. (See Figure 12.3 of the text.)
• The source, drain, and gate are the JFET counterparts of the BJT emitter, collector, and base (respectively).

 

FIGURE 12-2. JFET symbols.

The overall operation of the JFET is based on varying the width of the channel to control the drain current, as follows: Conduction varies inversely with the cross-sectional area of a conductor. As shown in Figure 12-3, the current in the drain-source circuit passes through the JFET channel. By narrowing the effective width of the channel, conduction through the drain-source circuit can be controlled.

 

FIGURE 12-3. JFET conduction.

The width of the JFET channel is decreased by increasing the effective width of the gate. The effective width of the gate can be increased by applying a reverse gate-source voltage (), as shown in Figure 12-4. Applying a reverse gate-source voltage causes a depletion layer to be formed around the gate (as shown in the figure), reducing the current through the drain-source circuit.

 

FIGURE 12-4. The effect of applying a reverse gate-source voltage.

The gate junction can also be reverse biased by the drain-source voltage (). In Figure 12-5, the gate is shorted to the source. As a result, the gate is connected to the negative side of . Since the positive side of is connected to the drain, the n-type drain is more positive than the p-type gate, resulting in a small depletion layer being formed as shown.

 

FIGURE 12-5. Depletion layer formed by .

Pinchoff Voltage () and Shorted-Gate Drain Current ()

The voltage source () in Figure 12-5 generates a current through the JFET channel. As increases in value, the device current and the width of the depletion layer also increase. Once reaches a specified value, called the pinch-off voltage (), further increases in are offset by directly proportional increases in channel resistance and the device current levels off (becomes constant). This relationship is illustrated by the graph in Figure 12.7 of the text. Note that the rating of a given JFET is measured at .
  When and , drain current reaches its maximum possible value. This value, called the shorted-gate drain current (), is provided on the specification sheet of a given JFET.

Gate-Source Cutoff Voltage()

There is a value of that causes drain current () to drop to approximately 0 A. This value of is called the gate-source cutoff voltage, . When , the depletion layer around the gate closes the channel, resulting in . Note that the and ratings of a JFET are always equal in magnitude (and opposite in polarity). For that reason, only one of the two values is typically listed on the specification sheet for a given JFET.

The gate of a JFET is always reverse biased (under normal operating circumstances). For this reason, the gate resistance of a JFET is extremely high, typically in the G range. This high gate impedance is the primary advantage that the JFET has over the BJT. When the gate terminal of a JFET is used as the component input, the high resistance of the gate presents virtually no load on the source.

It should be noted that the gate of the JFET is not designed to handle any significant amount of current. Therefore, care should be taken to ensure that the gate never becomes forward biased. If it does, even relatively small currents (in the mA range) can damage the component.

Figure 12-6 shows a typical JFET amplifier. Since the component has no input current, it has no beta rating. However, the output current () at a given value of can be calculated using the equation shown in the figure.

 

FIGURE 12-6. JFET circuit and transconductance curve.

When the equation is solved for a series of values, the results can be used to plot the transconductance curve for the JFET. A generic transconductance curve is shown in Figure 12-6. Note that the curve ends at the and ratings for the component. A JFET transconductance curve is plotted as demonstrated in Example 12.2 of the text. Note that:

• Most JFETs have minimum and maximum transconductance curves, as demonstrated in Example 12.3.
• The transconductance curves for a given JFET are used in the dc analysis of the biasing circuit.

Gate bias is the JFET counterpart of base bias. A gate bias circuit is shown (along with its dc bias line) in Figure 12-7.

 

FIGURE 12-7. Gate-bias circuit and bias line.

The dc bias line represents all of the possible Q-point values for a FET biasing circuit. As shown in the figure, the Q-point for a gate-bias circuit can fall anywhere between the points where the bias line intersects the two transconductance curves. As a result, the Q-point value of drain current is extremely unstable for gate bias. This is the primary drawback of using this simple circuit.

Self-bias is a more commonly used FET biasing circuit that uses a source resistor () to develop a negative gate-source voltage. A self-bias circuit is shown (along with its dc bias line) in Figure 12-8.

 

FIGURE 12-8. Self-bias circuit and dc bias line.

The bias line shows that can still fall within a relatively large range of values, but this range is significantly narrower than the one for a comparable gate-bias circuit. (This point is illustrated in Figure 12.24 of the text.) The dc bias line for a self-bias circuit is plotted as follows:

1. Plot the minimum and maximum transconductance curves for the JFET.
2. Choose any value of and determine the corresponding value of using
   
3. Plot the point found with the equation and draw a line from that point to the origin of the graph.

This procedure is demonstrated in Example 12.6 of the text. Since self-bias provides a more stable output than gate-bias, it is the preferred circuit of the two. (Self-bias also has the advantage of not requiring the use of a negative power supply to bias the gate-source junction.)

Voltage-divider bias is used to drastically reduce the possible variations in that are inherent with JFET amplifiers. A voltage-divider biased JFET amplifier is shown in Figure 12-9, along with the dc analysis relationships for the circuit.

 

FIGURE 12-9. Voltage divider bias.

The dc bias line for the voltage-divider bias circuit is shown in Figure 12-10. Note the slight variation in I_D between the Q-points. The relatively stable value of drain current is the strength of the circuit. The procedure used to plot the dc bias line is demonstrated in Example 12.8 of the text.

 

FIGURE 12-10. The dc bias line for a voltage-divider biased amplifier.

Current-source bias uses a BJT to control JFET drain current, making it independent of the JFET characteristics. A current-source bias circuit is shown in Figure 12-11. As long as the circuit is designed so that is less than the minimum value of , the Q-point value of drain current is independent of the JFET characteristics.

 

FIGURE 12-11. Current-source bias.

The common-source (CS) amplifier is the JFET counterpart of the common-emitter amplifier. As shown in Figure 12-12, the input is applied to the JFET gate and the output is taken from the drain. Note that the CS amplifier is the only JFET amplifier configuration that produces a 180° voltage phase shift from input to output.

The transconductance () of a JFET amplifier is the ratio of a change in drain current () to a change in gate-source voltage (), typically measured in microsiemens (). As the equation in Figure 12-12 implies, the value of is affected by the transconductance rating of the JFET () and the dc biasing of the circuit. This point is illustrated in Example 12.11 of the text.

 

FIGURE 12-12. Common-source amplifier.

The voltage gain of the standard CS amplifier falls within a range of values that is determined (in part) by the minimum and maximum transconductance curves for the device. This point is illustrated in Example 12.12 of the text. To overcome this problem a swamping resistor may be used.

The source follower is the JFET counterpart of the emitter follower. As shown in Figure 12-13, the input is applied to the JFET gate and the output is taken from the source.

FIGURE 12-13. Common-drain amplifier (source follower).

The source follower typically has high input impedance, low output impedance, and . As a result, the circuit is typically used as a buffer. The voltage gain and output impedance of the source follower fall within ranges that are determined (in part) by the minimum and maximum transconductance curves for the device. This point is illustrated in Example 12.16 of the text.

The common-gate (CG) amplifier is the JFET counterpart of the common-base amplifier. As shown in Figure 12-14, the input is applied to the JFET source and the output is taken from the drain.

 

FIGURE 12-14. Common-gate amplifier.

The CG amplifier typically has low input impedance, high output impedance (as compared to , and ). As a result, the circuit is typically used to match a low-impedance source to a higher-impedance load. Note that the JFET output admittance () is a spec sheet rating. The output impedance of the CG amplifier is calculated as demonstrated in Example 12.17 of the text.

There are few things that can go wrong with a JFET. Since there is only one component junction, the symptoms of a JFET fault are easy to recognize. The effects of shorted-gate and open-gate conditions are illustrated in Figure 12.47 of the text.

Like transistor spec sheets, JFET spec sheets typically list maximum ratings, off characteristics, on characteristics, and small-signal characteristics.

The maximum ratings section of the JFET spec sheet typically includes the standard breakdown voltage ratings, maximum current ratings, and temperature operating ranges.

The off characteristics section of the spec sheet typically lists the values of , gate-source breakdown voltage, and gate reverse current. Note that gate reverse current () is typically in the nA or range.

The on characteristics section of the spec sheet typically lists the value of and a minimum possible value of .

The small-signal characteristics section of the spec sheet typically lists the component conductance, admittance, transconductance, and transadmittance ratings. Note that the admittance ratings take the component susceptance into account, whereas the conductance ratings do not.

JFETs are typically used in any application requiring higher circuit input impedance than can be obtained with a BJT amplifier.

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